As application demands increase, a few trends are coming to the fore:

• Single-threaded performance bumps don’t suffice to boost application performance.
• Data in use memory limitations are resulting in designers looking for memory expansion with new memory links and memory types.
• Computer architecture designers have long advocated the use of domain-specific accelerators and data movement accelerators

Given the diversity of accelerator and memory technologies, standardizing memory to memory data movement and acceleration that is independent of interconnect and implementation form factors is needed.

SNIA's Smart Data Accelerator Interface(SDXI) Technical Working Group(TWG) is at the forefront of standardizing this as it works towards a v1.0 release of SNIA SDXI specification.

In addition to standardizing an architectural memory-to-memory data movement interface, SDXI is seen as a key enabler technology for persistent memory technologies and computational storage use cases.

This talk will summarize various use cases/application acceleration patterns SDXI enables, the features discussed in the SDXI v0.9-rev1 specification out for public review, and SNIA's efforts around standardizing this work.

For 30 years, PCI-SIG® has supported industry IO needs by developing specifications and delivering a predictable path through to implementation compliance. PCI-SIG defines the PCI Express® (PCIe®) I/O specifications and related form factors, with 900+ member companies located worldwide.

This talk will provide an overview of PCI-SIG itself and PCIe, the status and key features for PCIe 5.0, 6.0 and planned 7.0 specifications, and will touch upon current and future areas for collaboration between our organizations.

CXL™ is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices. This talk will explore the features and benefits of CXL and review new features added in the 2.0 specification and subsequent ECNs including support for switching, persistent memory and improvements in the areas of device management, RAS, security, and memory interleaving.